Fujitsu F2MC-16LX Hardware Manual page 70

CHAPTER 3 INTERRUPTS
Table 3.2-1 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers (2/2)
Interrupt cause
Input capture (ch.0)
incorporation (input timer)
Input capture (ch.1)
incorporation (input timer)
Input capture (ch.2)
incorporation (input timer)
Input capture (ch.3)
incorporation (input timer)
Output compare (ch.0)
unification (output timer)
Output compare (ch.1)
unification (output timer)
Output compare (ch.2)
unification (output timer)
Output compare (ch.3)
unification (output timer)
UART has been sent
2
I C interface 0
UART has been received
2
I C interface 1
Flash memory status
Delay interrupt
Y1: An interrupt request flag is cleared by the EI
Y2: An interrupt request flag is cleared by the EI
N: An interrupt request flag is not cleared by the EI
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Interrupt vector
2
EI OS clear
Number
Y2 #29
Y2 #30
Y2 #31
Y2 #32
Y2 #33
Y2 #34
Y2 #35
Y2 #36
Y2 #37
N #38
Y1 #39
N #40
N #41
N #42
2
OS interrupt clear signal. There is a stop request.
2
OS interrupt clear signal.
2
OS interrupt clear signal.
Interrupt control register
Address Number
FFFF88
H
ICR09
FFFF84
H
FFFF80
H
ICR10
FFFF7C
H
FFFF78
H
ICR11
FFFF74
H
FFFF70
H
ICR12
FFFF6C
H
FFFF68
H
ICR13
FFFF64
H
FFFF60
H
ICR14
FFFF5C
H
FFFF58
H
ICR15
FFFF54
H
Address
0000B9
H
0000BA
H
0000BB
H
0000BC
H
0000BD
H
0000BE
H
0000BF
H