Fujitsu F2MC-16LX Hardware Manual page 191

Figure 10.4-2 Clearing the Counter by a Compare Match with output Compare Register 0
Counter value
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Reset
Compare register
value
Interrupt
■ 16-bit Free-run Timer Count Timing
The 16-bit free-run timer is counted up with an input clock.
φ
Machine clock
" "
Clock input
Count clock
Counter value
The counter can be cleared by a reset, software, or a match with compare register 0. The
counter clear by the reset or software is executed simultaneously with clear generation.
However, the counter clear by a match with compare register 0 is executed synchronously with
the count timing.
Figure 10.4-4 Clear Timing of the Free-run Timer (Match With Compare Register 0)
φ
Machine clock " "
Compare register
value
Compare match
Counter value
Figure 10.4-3 Count Timing of the Free-run Timer
N
N
N
10.4 16-Bit Free-Run Timer Operations
Match
BFFF
H
Match
N+1
0000
Time
175