Bus Status Register (Ibsr) - Fujitsu F2MC-16LX Hardware Manual

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CHAPTER 19 I C INTERFACE

19.3.1 Bus Status Register (IBSR)

The bus status register (IBSR) shows the status of each function of the I
■ Bus Satus Rgister (IBSR)
Bus status register
Address:
ch .0 00002C
ch.1 000032
Read/write
Initial value
[bit7] BB (Bus busy)
The BB bit shows the status of the I
Table 19.3-1 Functions of the BB (Bus Busy) Bit
BB
0
1
[bit6] RSC (Repeated start condition)
The RSC bit detects the repeated start condition. This bit is cleared when (1) "0" is written to
the INT bit, (2) no addressing was made in slave mode, (3) the start condition is detected
while the bus stops, or (4) the stop condition is detected.
Table 19.3-2 Functions of the RSC (Repeated Start Condition) Bit
RSC
0
1
[bit5] AL (Arbitration lost)
The AL bit detects an arbitration loss.
This bit is cleared by writing "0" to the INT bit.
Table 19.3-3 Functions of the AL (Arbitration Lost) Bit
AL
0
1
306
Figure 19.3-2 Bus status register (IBSR)
7 6
bit
H
BB RSC
H
(R) (R) (R)
( 0) ( 0) ( 0)
Stop condition is detected. [Initial value]
Start condition is detected. (This means the bus is in use.)
Repeated start condition is not detected. [Initial value]
Start condition is detected again while the bus is in use.
No arbitration loss is detected. [Initial value]
Either an arbitration loss has occurred during transmission by the master, or
"1" has been written to the MSS bit while another system is using the bus.
5 4 2
3
AL LRB TRX AAS
(R) (R) (R)
( 0) ( 0) ( 0)
2
C bus.
Status of the I
Status of the start condition detection
Status of the arbitration loss detection
2
C interface.
1 0
GCA FBT
(R) (R)
( 0) ( 0)
2
C bus
IBSR