8/16-Bit Ppg Operation - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 12 8/16-BIT PPG

12.4 8/16-Bit PPG Operation

The 8/16-bit PPG contains two 8-bit PPG units and can operate in the 8-bit 2-ch mode
and in two other operation modes, including the 8-bit prescaler + 8-bit PPG mode and
the 16-bit PPG 1-ch mode, where the two PPG units interact.
Here, ch.0 and ch.1 are used as an example. For ch.2 and ch.4, replace ch.0 in the
explanation with ch.2 or ch.4. For ch.3 and ch.5, replace ch.1 in the explanation with
ch.3 or ch.5.
■ 8/16-bit PPG Operation
For each of the 8-bit PPG units, two 8-bit reload registers (PRLL and PRLH ) are provided for
the lower and higher data. The value for the lower data and the value for the higher data written
in these registers are alternately reloaded into the 8-bit down counter (PCNT), which counts
down on each clock pulse. At a reload operation performed when a borrow is generated in the
counter, the pin output (PPG) value is inverted. This operation allows the pin output (PPG) to
output a pulse signal with low-level and high-level widths corresponding to the reload register
values.
Operation is started and restarted by writing an appropriate register bit.
The relationship between reload operation and pulse output is shown in Table 12.4-1.
Table 12.4-1 Relationship between Reload Operation and Pulse Output
PRLH --> PCNT
PRLL --> PCNT
When the PIE0 bit of the PPGC0 register is "1" and when the PIE1 bit of the PPGC1 register is
"1", a borrow from 00
mode) causes an interrupt request to be output.
■ 8/16-bit PPG Interrupt
An interrupt of the 8/16-bit PPG becomes active when the counter counts out the reloaded
value, generating a borrow.
In the 8-bit PPG 2-ch mode and in the 8-bit prescaler + 8-bit PPG mode, a borrow into each
counter causes a relevant interrupt request. In the 16-bit PPG mode, a borrow into the 16-bit
counter sets the PUF0 bit and PUF1 bit at the same time. It is recommended that only one of
the PIE0 and PIE1 bits be enabled to determine a single interrupt source.
recommended that the interrupt source be cleared by resetting the PUF0 bit and PUF1 bit at the
same time.
206
Reloading
0 --> 1
1 --> 0
to FF in each counter (a borrow from 0000
H H
Status transition of output pins PPG0 and PPG1
to FFFF in the 16-bit PPG
H H
It is also