Fujitsu F2MC-16LX Hardware Manual page 185

■ Control Status Register (OCS0 to OCS2)
Compare control
status register 1/3
Address: ch.1 000079
ch.3 00007B
Read/write
Initial value
Compare control
status register 0/2
Address: ch.0 000078
ch.2 00007A
Read/write
Initial value
[bit12] CMOD
CMOD switches the pin output level reverse operation mode for a compare match when pin
output is allowed (OTE1 = 1 or OTE0 = 1).
❍ For CMOD = 0 (initial value)
When CMOD is "0" (initial value), the output level of the pin corresponding to the compare
register is reversed.
• OUT0: Reverses the level by a match with compare register 0.
• OUT1: Reverses the level by a match with compare register 1.
❍ For CMOD = 1
When CMOD is "1", the output level of the pin (OUT0) corresponding to the compare register 0
is reversed in the same way as when CMOD is "0". However, the output level of the pin (OUT1)
corresponding to the compare register 1 is reversed by both a match with compare register 0
and a match with compare register 1. If values of compare registers 0 and 1 are equal, the
operation is the same as when one compare register is used.
• OUT0: Reverses the level by a match with compare register 0.
• OUT1:Reverses the level by both a match with compare register 0 and a match with
[bit11, bit10] OTE1 and OTE0
OTE1 and OTE0 bits enable the pin output of the output compare.
Table 10.3-7 Function of OTE1 and OTE0 (Pin Output Enable Bits)
OTE1, OTE0
0
1
Note:
OTE1 corresponds to output compare 1 and OTE0 to output compare 0.
Figure 10.3-5 Control Status Register
15 14 13
bit
H
H
(-) (-) (-)
(-) (-) (-)
7 6
bit
H
IOP1 IOP0 IOE1
H
(R/W) (R/W) (R/W) (R/W)
(0) (0) (0)
compare register 1.
Operates as a general-purpose port. [Initial value]
Enables the output compare pin output.
12 11 10
CMOD OTE1 OTE0 OTD1 OTD0
(R/W) (R/W) (R/W) (R/W) (R/W)
(0) (0) (0)
5 4 2
3
IOE0
(-) (-)
(0) (-) (-)
Function
10.3 16-Bit I/O Timer Registers
9
8
OCS1/OCS3
(0) (0)
1 0
CST1 CST0 OCS0/OCS2
(R/W) (R/W)
(0) (0)
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