Fujitsu F2MC-16LX Hardware Manual page 10

CHAPTER 4 GENERATING AND RESETTING CLOCKS ............................................. 81
4.1 Clock Generator ................................................................................................................................ 82
4.2 Clock Supply Map ............................................................................................................................. 83
4.3 Reset Causes ................................................................................................................................... 84
4.4 Operation after a Reset is Released ................................................................................................. 86
4.5 Registers not Initialized by Reset Input ............................................................................................ 87
CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT .............................. 89
5.1 Overview of the Low-power Consumption Control Circuit ................................................................ 90
5.2 Low-power Consumption Mode Control Register (LPMCR) ............................................................. 93
5.3 Clock Selection Register (CKSCR) ................................................................................................... 95
5.4 Operation of the Low-power Consumption Control Circuit ............................................................... 98
5.4.1 Sleep Mode ............................................................................................................................... 100
5.4.2 Watch Mode .............................................................................................................................. 101
5.4.3 Stop Mode ................................................................................................................................. 103
5.4.4 Hardware Standby Mode ........................................................................................................... 104
5.4.5 Pin status in the Sleep, Stop, Hold, Reset, and Hardware Standby Modes .............................. 105
5.5 Intermittent CPU Operation Function .............................................................................................. 108
5.6 Setting the Oscillation Stabilization Time ........................................................................................ 109
5.7 Machine Clock ................................................................................................................................ 110
CHAPTER 6 MEMORY ACCESS MODES .................................................................... 113
6.1 Memory Access Mode Overview .................................................................................................... 114
6.1.1 Mode Pins .................................................................................................................................. 115
6.1.2 Mode Data ................................................................................................................................. 116
6.1.3 Memory Space for Each Bus Mode ........................................................................................... 117
6.2 External Memory Access (External Bus Pin Control Circuit) .......................................................... 120
6.2.1 Registers for External Memory Access (External Bus Pin Control Circuit) ................................ 121
6.2.2 Automatic Ready Function Selection Register (ARSR) ............................................................. 122
6.2.3 External Address Output Control Register (HACR) ................................................................... 124
6.2.4 Bus Control Signal Selection Register (ECSR) ......................................................................... 125
6.3 Operation of the External Memory Access Control Signals ............................................................ 128
6.3.1 Ready Function ......................................................................................................................... 130
6.3.2 Hold Function ............................................................................................................................ 132
CHAPTER 7 I/O PORTS ................................................................................................ 133
7.1 I/O Port Overview ........................................................................................................................... 134
7.2 I/O Port Block Diagram ................................................................................................................... 135
7.3 I/O Port Registers ........................................................................................................................... 138
7.3.1 Port Data Registers (PDRx) ...................................................................................................... 140
7.3.2 Port Data Direction Registers (DDRx) ....................................................................................... 142
7.3.3 Output Pin Register (ODR4) ...................................................................................................... 143
7.3.4 Input Resistor Registers (RDR0 and RDR1) ............................................................................. 144
7.3.5 Analog Input Enable Register (ADER) ...................................................................................... 145
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