Fujitsu F2MC-16LX Hardware Manual page 145

Figure 6.3-2 Timing Chart of External Data Bus 16-bit Mode Access (for 16-bit Bus Width Access and 8-
P37/CLK
P33/WRH
P32/WRL
P31/RD
P30/ALE
P27~P20/A23~A16
P17~P10/AD15~AD08
P07~P00/AD07~AD00
P37/CLK
P33/WRH
P32/WRL
P31/RD
P30/ALE
P27~P20/A23~A16
P17~P10/AD15~AD08
P07~P00/AD07~AD00
P37/CLK
P33/WRH
P32/WRL
P31/RD
P30/ALE
P27~P20/A23~A16
P17~P10/AD15~AD08
P07~P00/AD07~AD00
Design external circuits so that data is always read in units of word length.
Access to low-speed memory and peripheral circuits is enabled by setting of
the P36/RDY pin or the automatic ready function selection register (ARSR).
6.3 Operation of the External Memory Access Control Signals
bit Bus Width Access)
8-bit bus byte read
Even-numbered
address byte read
Read address
Read address Invalid
Read address
Odd-numbered
address byte read
Read address
Read address
Read address Invalid
Even-numbered
address word read
Read address
Read address
Read address
8-bit bus byte write
Even-numbered
address byte write
Write address
Write address
Write address
Read data Write data
Odd-numbered
address byte write
Write address
Write address
Write address
Read data Write data
Even-numbered
address word write
Write address
Write address
Write address
Read data Write data
Read address
(Not defined) Read address
Read address
Read address
Read address
(Not defined) Read address
Read address
Read address
Read address
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