Fujitsu F2MC-16LX Hardware Manual page 238

CHAPTER 13 DTP/EXTERNAL INTERRUPT
generates a signal for clearing the source of the transfer. When receiving the signal for clearing
the transfer source, this resource clears the flip-flop that holds the source and is made ready for
another request from a pin.
Figure 13.3-2 Timing for Canceling an External Interrupt Request when DTP Operation Terminates
Interrupt source
Internal operation
Address bus pin
Data bus pin
Read signal
Write signal
Figure 13.3-3 Schematic of a Sample Interface with an External Peripheral Device
Data and
address buses
IRQ
To be canceled within 3
machine cycles after the
end of a transfer
■ Switching between an External Interrupt Request and a DTP Request
Switching between an external interrupt request and a DTP request is performed by setting the
ISE bit of an ICR register for this resource. ICR registers are in the interrupt controller.
A separate ICR register is assigned to each pin. When the ISE bit of the ICR for a pin is set to
"1", the pin functions as a DTP request. When the ISE bit is set to "0", the pin functions as an
external interrupt request.
222
Rising-edge request or high-level request
Descriptor
selection and read
DTP
MB90550A/B
*When extended intelligent I/O service is
a transfer from I/O register to memory
Read address Write address
Read data
To be canceled within 3 machine cycles
Internal bus
INT
CORE
Write data
MEMORY