Fujitsu F2MC-16LX Hardware Manual page 284

CHAPTER 17 UART
Table 17.3-14 Function of FRE (Framing Error)
FRE
0
1
[bit12] RDRF (Receiver data register full)
The RDRF bit is an interrupt request flag indicating that the SIDR register is full with receiver
data. The bit is set when receiver data is loaded into the SIDR register and automatically
cleared when the data is read from the SIDR register.
Table 17.3-15 Function of RDRF (Receiver Data Register Full)
RDRF
0
1
[bit11] TDRE (Transmitter data register empty)
The TDRE bit is an interrupt request flag indicating that transmitter data can be written into
the SODR register. Once the data is written into the SODR register, the bit is cleared.
When the written data is loaded into the transmitter shifter and transfer is started, the bit is
set again, indicating the next transmitter data can be written.
Table 17.3-16 Function of TDRE (Transmitter Data Register Empty)
TDRE
0
1
[bit9] RIE (Receiver interrupt enable)
The RIE bit controls a receiver interrupt.
Table 17.3-17 Function of RIE (Receiver Interrupt Enable)
RIE
0
1
Note:
Receiver interrupt sources include the occurrence of a PF, ORE, or FRE error and normal
reception by RDRF.
268
No framing error [Initial value]
Framing error occurs.
Register is not full with receiver data. [Initial value]
Register is full with receiver data.
Transmitter data cannot be written.
Transmitter data can be written. [Initial value]
Disables an interrupt. [Initial value]
Enables an interrupt.
Function
Function
Function
Function