Fujitsu F2MC-16LX Hardware Manual page 201

The MOD1 and MOD0 bits are used to set a pin function in each mode.
Table 11.2-2 Functions of MOD2, MOD1, and MOD0 (for Setting an Operation Mode and I/O Pin
Function)
Mode
Internal clock mode
(CSL0, CSL1=00,
01, 10)
Event count mode
(CSL0, CSL1=11)
× : Any value
[bit6] OUTE
The OUTE bit enables the output.
• When this bit is "0", the TOT pin is used as the general-purpose port.
• When this bit is "1", the TOT pin is used as the timer output pin.
[bit5] OUTL
The OUTL bit sets the output level of the TOT pin.
[bit4] RELD (Reload)
The RELD bit enables the reload operation.
• When this bit is "0", a one-shot operation mode is entered. The count operation stops with
the underflow of the counter value from 0000
• When this bit is "1", a reload mode is entered. An underflow of the counter value from 0000
to FFFF
counter. The count operation continues.
Table 11.2-3 Function of RELD (reload operation enable bit)
OUTE
0
1
1
1
1
× : Any value
11.2 Registers of the 16-Bit Reload Timer (with the Event Count Function)
MOD2 MOD1
0 0
0 0
0 1
0 1
1 ×
1 ×
0
0
×
1
1
occurs and, at the same time, the contents of the reload register are loaded to the
H
OUTL
×
0
0
1
1
MOD0 I/O pin function
0 Trigger disabled
1
0 Trigger input
1
0
Gate input
1
0 -
1
0 Trigger input
1
to FFFF .
H H
RELD
× General-purpose port
0 Rectangular wave of H during counting
1 Toggle output of L at count start
0 Rectangular wave of L during counting
1 Toggle output of H at count start
Valid edge, level
-
Rising edge
Falling edge
Both edges
"L" level
"H" level
-
Rising edge
Falling edge
Both edges
Output waveform
H
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