Fujitsu F2MC-16LX Hardware Manual page 212

CHAPTER 12 8/16-BIT PPG
Figure 12.2-2 Block Diagram of the 8-bit PPG (ch.1/ch.3/ch.5)
Machine clock divided by 16
Machine clock divided by 8
Machine clock divided by 4
Machine clock divided by 2
Machine clock
ch.0/ch.2/ch.4:
Borrow
PCNT (down counter)
Time-based timer
(output oscillation clock
divided by 512)
L/H selection
196
PPG1/3/5
output latch
Inversion
Clear
Count clock
selection
Reload
L/H selector
PRLL1/3/5 PRLBH1/3/5
PRLH1/3/5
PPG1/3/5 output enabled
PEN1/3/5
S
R Q
PIE1
PUF1
PPGC1/3/5
(Operation mode control)
PPG1/3/5
IRQ
Lower Data Bus
Higher Data Bus