Operation States Of The Serial I/O - Fujitsu F2MC-16LX Hardware Manual

18.3.2 Operation States of the Serial I/O

The serial I/O supports the following four operation states:
• STOP state
• Suspend state
• SDR register R/W wait state
• Transfer state
■ STOP State
At a reset or when writing 1 to the STOP bit of SMCS, the shift counter is initialized and SIR = 0
is set. To recover from the stop state, set STOP = 0 and STRT = 1 (specifiable at the same
time). The STOP bit has higher priority than the STRT bit. Therefore, while STOP = 1, STRT =
1 cannot start the transfer operation.
■ Suspend State
When the MODE bit is 0, terminating a transfer sets BUSY = 0 and SIR = 1 in the SMCS
register, initializes the counter, and changes to the suspend state. To recover from the suspend
state, set STRT = 1. Then the transfer operation restarts.
■ Serial Data Register R/W Wait State
When the MODE bit of the SMCS register is "1", if a serial transfer terminates, BUSY = 0 and
SIR = 1 are set and the serial I/O changes to the SDR register R/W wait state. If the interrupt
enable register allows an interrupt, this block sends an interrupt signal.
To recover from the R/W wait state, read or write the SDR register to set BUSY = 1. The
transfer operation then restarts.
■ Transfer State
In this state, BUSY = 1 and the serial transfer is being executed. This state transits to the
suspend or R/W wait state depending on the MODE bit.
Figure 18.3-1 shows the transition of the operation states of the I/O extended serial interface.
Figure 18.3-2 shows the concept of reading and writing to the serial data register.
18.3 Operation of I/O Extended Serial Interface
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