Fujitsu F2MC-16LX Hardware Manual page 75

■ Hardware Interrupt Request during Writing to the Internal Resource Area
No hardware interrupt requests are accepted during writing to the internal resource area. This
was implemented to prevent CPU malfunctions due to interrupt conflicts in connection with
overwriting the interrupt control registers for each resource.
represents the area allocated to the control register or data register of the internal resource
rather than the I/O addressing area of 000000
Figure 3.4-1 Hardware interrupt request during writing to the internal resource area
■ Interrupt Stop Instruction
See Section "2.7 Interrupt Suppression Instructions and Prefix Codes".
■ Multiple Interrupts
2
The F MC-16LX CPU supports multiple interrupts. If an interrupt with a higher level than a
currently processed interrupt occurs, control is transferred to the interrupt with the higher level
after finishing the currently executed instruction. After completing the execution of this interrupt,
the control returns to the execution of the previous interrupt. If an interrupt with the same or a
lower level occurs during interrupt processing, the new interrupt is put on hold until the currently
processed interrupt is completed, unless the contents of the ILM are changed or the respective
interrupt levels change by an instruction to change the I flag. The extended intelligent I/O
service cannot be started multiple times simultaneously. While one instance of the extended
intelligent I/O service is being processed, all other interrupt requests and extended intelligent I/O
service requests are put on hold.
■ Saving a Register to the Stack at an Interrupt
MSB
H
DPR
DPB
L
Write instruction to the internal resource area
MOV A,#08 MOV io,A
An interrupt
request occurs
Figure 3.4-2 Registers Saved to the Stack
Word (16 bits)
AH
AL
ADB
PCB
PC
PS
to 0000FF .
H H
MOV A,2000H
No branching Branching to
to the interrupt. the interrupt
LSB
SSP
(Value of SSP before an interrupt occurs)
SSP
(Value of SSP after an interrupt occurs)
3.4 Hardware Interrupts
The internal resource area
Interrupt processing
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