Fujitsu F2MC-16LX Hardware Manual page 172

CHAPTER 9 WATCHDOG TIMER
Table 9.2-2 WT1 and WT0 (Interval Time Selection Bits)
WT1 WT0
0 0
0 1
1 0
1 1
Note:
Since the carry signal of the time-based timer is used as the count clock of interval time, the interval
time of the watchdog timer may become longer when the time-based timer is cleared.
Note that the time-based timer is cleared and "0" is written to the TBR bit of the time-based timer
control register (TBTC) during a transition from main clock mode to PLL clock mode.
156
Interval time (for oscillation clock frequency
4 MHz)
Minimum
Approx. 3.58 ms
Approx. 14.33 ms
Approx. 57.23 ms
Approx. 458.75 ms
Maximum
Approx. 4.61 ms
Approx. 18.43 ms
Approx. 73.73 ms
Approx. 589.82 ms
Number of oscillation
clock (oscillation)
cycles
14 ± 11
2 2
16 ± 13
2 2
18 ± 15
2 2
21 ± 18
2 2