Underflow Operation - Fujitsu F2MC-16LX Hardware Manual

11.4 Underflow Operation

The 16-bit reload timer (with the event count function) defines the following case as an
underflow: when a counter value changes 0000
Therefore, an underflow occurs with [reload register setting value + 1].
■ Underflow Operation
If an underflow occurs when the RELD bit of the control register is "1", the contents of the reload
register are loaded to the counter to continue the count operation. When the RELD bit of the
control register is "0", the counter stops with FFFF
control register is set. At this time, if the INTE bit is "1", an interrupt request is generated.
[For RELD = 1]
Count clock
Counter
Data load
Underflow set
[For RELD = 0]
Count clock
Counter
Underflow set
■ Extended Intelligent I/O Service (EI
This timer has a circuit associated with EI
underflow of this timer. For this product, both timers can use EI
Figure 11.4-1 Underflow Operation
Reload data
0000
H
0000 FFFF
H H
2
OS) Function and Interrupts
to FFFF .
H H
. If an underflow occurs, the UF bit of the
H
-1
2 2
OS. Therefore, EI OS can be activated by an
2
OS.
11.4 Underflow Operation
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