Registers In The Dtp/External Interrupt Circuit - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 13 DTP/EXTERNAL INTERRUPT

13.2 Registers in the DTP/External Interrupt Circuit

The ENIR register determines whether to use device pins as external interrupt/DTP
request inputs to initiate the function of issuing a request to the interrupt controller.
■ Interrupt/DTP Enable Register (ENIR)
Interrupt/DTP enable register
Address:000038
Read/write
Initial value
When a bit in the interrupt/DTP enable register (ENIR) is set to "1", the corresponding pin is
used as an external interrupt/DTP request input to initiate the function of issuing a request to the
interrupt controller. For a pin corresponding to a bit set to "0", an external interrupt/DTP request
input source is held, but no request is issued to the interrupt controller.
ENx corresponds to IRQx.
Note:
Please clear corresponding DTP/external interruption factor bit (EIRR:ER) immediately
before DTP/external interruption is permitted (ENIR:EN=1).
■ Interrupt/DTP Source Register (EIRR)
Interrupt/DTP source register
Address:000039
H
Read/write
Initial value
When the EIRR register is read from, it indicates that a corresponding external interrupt/DTP
request is present. When the register is written to, the flip-flop content indicating the request is
cleared. When "1" is read from a bit in this register, it indicates that an external interrupt/DTP
request is present on the pin corresponding to the bit.
When "0" is written to this register, the request flip-flop of the corresponding bit is cleared.
Writing "1" to this register causes no operation. At read in read-modify-write operation, "1" is
read.
ERx corresponds to IRQx.
218
Figure 13.2-1 Interrupt/DTP Enable Register (ENIR)
7 6 5
bit
EN7 EN6 EN5
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0) (0) (0)
Figure 13.2-2 Interrupt/DTP Source Register (EIRR)
15 14 13
bit
ER7 ER6 ER5
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X) (X) (X)
4 2 1
3
EN4 EN3 EN2 EN1
(0) (0) (0) (0)
12 11 10 9
ER4 ER3 ER2 ER1
(X) (X) (X) (X)
0
EN0 ENIR
(0)
8
ER0 EIRR
(X)