Fujitsu F2MC-16LX Hardware Manual page 280

CHAPTER 17 UART
Table 17.3-7 SBL (Stop Bit Length Specification Bit)
SBL
0
1
[bit12] CL (Character length)
The CL bit specifies the data length of one frame to be transmitted or received.
Table 17.3-8 CL (Transmitter or Receiver Data Length Specification Bit)
CL
0
1
Note:
7-bit data can be processed only in the normal mode (mode 0) of asynchronous (start-stop
synchronous) communication modes. In multiprocessor mode (mode 1) and CLK-synchronous
communication mode (mode 2), set the bit to "1".
[bit11] A/D (Address/data)
The A/D bit specifies a data format of a frame to be transmitted or received in the
multiprocessor mode (mode 1) of asynchronous (start-stop synchronous) communication
modes.
Table 17.3-9 Function of A/D (Address/Data) Bit
A/D
0
1
[bit10] REC (Receiver error clear)
Writing "0" to the REC bit clears the error flags (PE, ORE, and FRE) of the SSR register.
Writing "1" is invalid. The read value is always "1".
[bit9] RXE (Receiver enable)
The RXE bit controls a UART receive operation.
Table 17.3-10 Function of RXE (Receiver Enable) Bit
RXE
0
1
Note:
If the RXE is set to 0 during the receive operation (while inputting data into the receiver shift
register), the receive operation is stopped when the receiving of the frame is completed and
the receiver data is stored in the receiver data buffer SIDR register.
264
1 stop bit [Initial value]
2 stop bits
7-bit data [Initial value]
8-bit data
Data frame [Initial value]
Address frame
Disables a receive operation. [Initial value]
Enables a receive operation.
Function
Function
Function
Function