Fujitsu F2MC-16LX Hardware Manual page 79

■ Processing Time for a Hardware Interrupt
After an interrupt request occurs, receiving the interrupt and executing the interrupt processing
routine takes the time required to wait for the interrupt request sample and the interrupt handling
time.
❍ Time to wait for the interrupt request sample
This represents the time between the occurrence of an interrupt request up to the completion of
the currently executed instruction. Whether an interrupt request has occurred is determined by
sampling for interrupt requests in the last cycle of each instruction This leads to wait time.
The time to wait for an interrupt request sample is longest immediately after the POPW with the
longest execution cycle or when one of the instructions PW0 to PW7 (45 machine cycles) is
started.
❍ Interrupt handling time (time required to perform interrupt processing)
Interrupt start : 24 + 6 × (machine cycles according to Table 3.4-1)
Interrupt recover : 15 + 6 × (imachine cycles according to Table 3.4-1) (RETI instruction)
Table 3.4-1 Corrective Value of the Number of Cycles for Interrupt Processing
Address to which the stack pointer points
External area 8-bit data bus
External area even-numbered address
External area odd-numbered address
Internal area even-numbered address
Internal area odd-numbered address
3.4 Hardware Interrupts
Corrective value of the
number of cycles
+4
+1
+4
0
+2
63