Fujitsu F2MC-16LX Hardware Manual page 482

INDEX
Reload Register
Reload Registers (PRLL/PRLH) ........................ 205
Reload Registers
Write Timing for the Reload Registers ............... 213
Reload Timer
Block Diagram of the 16-bit Reload Timer
(with the Event Count Function) ........... 182
Overview of the 16-bit Reload Timer
(with the Event Count Function) .......... 182
Registers of the 16-bit Reload Timer
(with the Event Count Function) .......... 183
Reloaded Value
Relationship between the Reloaded Value and
Pulse Width ........................................ 210
Request Level Setting Register
Request Level Setting Register (ELVR) ............. 219
Reset
Operation after a Reset is Released ...................... 86
Preventing a Watchdog Timer Reset .................. 157
Registers not Initialized by Reset Input................. 87
Reset Causes...................................................... 84
Setting the Flash Memory to the Read or Reset Status
.......................................................... 358
Reset Causes
Reset Causes...................................................... 84
Rgister
Bus Satus Rgister (IBSR) .................................. 306
ROM Mirror Function Selection Module
Block Diagram of the ROM Mirror Function Selection
Module............................................... 338
ROM Mirror Function Selection Register
ROM Mirror Function Selection Register (ROMM)
.......................................................... 339
ROMM
ROM Mirror Function Selection Register (ROMM)
.......................................................... 339
RP
Register Bank Pointer (RP) ................................. 37
S
SCC
Competition Among the SCC,MSS,and INT Bits
.......................................................... 311
SCR
Serial Control Register (SCR)............................ 263
Screening Conditions
Screening Conditions Recommended
for the OTPROM ................................ 454
SDR
Serial Shift Data Register (SDR) ......................... 291
Sector
Procedure for Deleting a Sector
from the Flash Memory........................ 362
466
Sector Deletion
Flash Memory from which any Data Item is Deleted
(Sector Deletion)................................. 362
Restarting the Flash Memory Sector Deletion
......................................................... 365
Temporarily Stopping the Sector Deletion
from the Flash Memory ....................... 364
Sector Deletion Timer Flag
Sector Deletion Timer Flag (DQ3)..................... 356
Serial Clock Input Frequency
Oscillating Clock Frequency and Serial Clock Input
Frequency .......................................... 374
Serial Control Register
Serial Control Register (SCR) ........................... 263
Serial Data Register R/W Wait State
Serial Data Register R/W Wait State.................. 295
Serial Input Data Register
Configuration of Serial Input Data Register (SIDR)
and Serial Output Data Register (SODR)
......................................................... 266
Serial Mode Control Status Register
Serial Mode Control Status Register (SMCS)
......................................................... 287
Serial Mode Register
Serial Mode Register (SMR) ............................. 261
Serial Output Data Register
Configuration of Serial Input Data Register (SIDR)
and Serial Output Data Register (SODR)
......................................................... 266
Serial Programming Connection
Basic Configuration of MB90F553A Serial
Programming Connection .................... 372
Example of Serial Programming Connection
(when Power is Supplied from a Writer)
......................................................... 377
Example of Serial Programming Connection
(when User Power Supply is Used)
......................................................... 375
Serial Shift Data Register
Serial Shift Data Register (SDR) ....................... 291
Serial Status Register
Serial Status Register (SSR).............................. 267
Shift Operation
Start/Stop Timing of Shift Operation and Input/Output
Timing............................................... 297
SIDR
Configuration of Serial Input Data Register (SIDR)
and Serial Output Data Register (SODR)
......................................................... 266
Single Chip Mode
Status of Each Pin in the Single Chip Mode
......................................................... 105