Fujitsu F2MC-16LX Hardware Manual page 327

Table 19.3-15 Functions of the INTE (Interrupt Enable) Bit
INTE
0
1
[bit8] INT (Interrupt)
The INT bit is for the interrupt request flag for transmission termination. When this bit is "1",
the SCL line stays at L level. The next byte is transmitted after this bit is cleared by writing
"0" and the SCL line is released. In master mode, generation of the start or stop condition
resets this bit to "0".
Table 19.3-16 Functions of the INT (Interrupt) Bit
When writing
When reading
■ Competition Among the SCC, MSS, and INT Bits
When the SCC, MSS, and INT bits are written to at the same time, competition occurs among
subsequent byte transmission and start and stop condition generation. The bits are prioritized
as follows:
1) Transmission of the next byte and stop condition generation
When "0" is written to the INT bit and MSS bit, the MSS bit takes precedence and the
stop condition is generated.
2) Transmission of the next byte and start condition generation
When "0" is written to the INT bit and "1" to the SCC bit, the SCC bit takes precedence
and the start condition is generated.
3) Start condition generation and stop condition generation
It is not permitted to write "1" to the SCC bit and "0" to the MSS bit at the same time.
Interrupts are disabled. [Initial value]
Interrupts are enabled.
INT
Clears the interrupt request flag for transmission termination.
0
[Initial value]
1 No meaning
0 The transmission is not terminated. [Initial value]
This is set when transmission of one byte including the
acknowledgment bit is terminated and any of the following
conditions occur:
• The device is the bus master.
1 • The device is the addressed slave.
• The general call address is received.
• An arbitration loss has occurred.
• An attempt was made to generate the start condition while
another system is using the bus.
19.3 Registers of the I
Function
Function
2
C Interface
311