Fujitsu F2MC-16LX Hardware Manual page 127

Figure 5.7-1 Status Transition Diagram for Clock Selection
Power-on
Main
(1)
MCS = 1
MCM= 1
CS1/CS0 = xx
(1) The MCS bit is cleared.
(2) The oscillation stabilization time for the PLL clock has elapsed and CS1, CS0 bit = 00.
(3) The oscillation stabilization time for the PLL clock has elapsed and CS1, CS0 bit = 01.
(4) The oscillation stabilization time for the PLL clock has elapsed and CS1, CS0 bit = 10.
(5) The oscillation stabilization time for the PLL clock has elapsed and CS1, CS0 bit = 11.
(6) The MCS bit is set (including a hardware standby or watchdog reset).
(7) The PLL clock synchronizes with the main clock.
Main
PLLx
MCS = 0
MCM= 1
(6)
CS1/CS0 = xx
(7)
Main
PLL1
MCS = 1
MCM= 0
CS1/CS0 = 00
(7)
Main
PLL2
MCS = 1
MCM= 0
(7)
CS1/CS0 = 01
Main
PLL3
MCS = 1
(7)
MCM= 0
CS1/CS0 = 10
Main
PLL4
MCS = 1
MCM= 0
CS1/CS0 = 11
(2)
(3)
PLL multiplication
factor: 1
(4)
MCS = 0
MCM= 0
(6)
CS1/CS0 = 00
PLL multiplication
factor: 2
MCS = 0
(6) MCM= 0
CS1/CS0 = 01
PLL multiplication
(5)
factor: 3
MCS = 0
MCM= 0
(6)
CS1/CS0 = 10
PLL multiplication
factor: 4
MCS = 0
MCM= 0
(6)
CS1/CS0 = 11
5.7 Machine Clock
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