Fujitsu F2MC-16LX Hardware Manual page 479

L
Latch
Note on Use of the Delayed Interrupt Request Latch
.......................................................... 229
Level
External Interrupt Request Level ....................... 224
Linear Addressing Methods
Linear Addressing Methods ................................ 27
Low-power Consumption Control Circuit
Block Diagram of the Low-power Consumption
Control Circuit...................................... 92
Operation of the Low-power Consumption Control
Circuit.................................................. 98
Overview of the Low-power Consumption Control
Circuit.................................................. 90
Low-power Consumption Mode Control Register
Low-power Consumption Mode Control Register
(LPMCR) ............................................. 93
LPMCR
Low-power Consumption Mode Control Register
(LPMCR) ............................................. 93
M
Machine Clock
Machine Clock Initialization ............................. 110
Switching the Machine Clock............................ 110
MB90F553A
Basic Configuration of MB90F553A Serial
Programming Connection .................... 372
Memory Access Mode
Memory Access Mode Overview....................... 114
Memory Space
Allocating Multiple-byte Data in a Memory Space
............................................................ 30
Memory Space................................................... 26
Memory Space for Each Bus Mode.................... 117
Recommended Setting Sample of Memory Space
for Each Bus Mode............................. 118
Minimal Connection
Example of Minimal Connection with the Flash
Microcontroller Programmer
(when Power is Supplied from a Writer)
.......................................................... 381
Example of Minimal Connection with the Flash
Microcontroller Programmer
(when User Power Supply is Used)
.......................................................... 379
Mode
Application of UART (During Operation in Mode 1)
.......................................................... 280
2
OS Activation in Pause Mode
Example of EI
.......................................................... 248
2
Example of EI OS Activation in Single Mode
.......................................................... 244
2
Example of EI OS Activation in Successive Mode
..........................................................246
External Shift Clock Mode ................................293
Flash Memory Mode.........................................345
2
C Interface Modes ........................321
Flow of the I
Input Pin Function (for the Internal Clock Mode)
..........................................................190
Internal Shift Clock Mode .................................293
Memory Access Mode Overview .......................114
Memory Space for Each Bus Mode ....................117
Other Modes ....................................................345
Pause Mode .....................................................243
Programming Mode ..........................................454
Recommended Setting Sample of Memory Space
for Each Bus Mode ..............................118
Releasing the Hardware Standby Mode...............104
Releasing the Sleep Mode .................................100
Releasing the Stop Mode ...................................103
Releasing the Watch Mode ................................101
Single Mode.....................................................242
Status of Each Pin in the External Bus 16-bit Data Bus
Mode..................................................106
Status of Each Pin in the External Bus 8-bit Data Bus
Mode..................................................107
Status of Each Pin in the Single Chip Mode
..........................................................105
Successive Mode ..............................................242
Transition to the Hardware Standby Mode ..........104
Transition to the Sleep Mode .............................100
Transition to the Stop Mode...............................103
Transition to the Watch Mode............................101
Mode Data
Mode Data .......................................................116
Mode Pins
Mode Pins........................................................115
MSS
Competition Among the SCC,MSS,and INT Bits
..........................................................311
Multiple Interrupt
Multiple Interrupts..............................................59
Multiple-byte Data
Access of Multiple-byte Data...............................30
Allocating Multiple-byte Data in a Memory Space
............................................................30
N
NCC
Flag Change Suppression Prefix (NCC) ................45
O
OCCP
Compare Register (OCCP0 and OCCP1) ............168
OCS
Control Status Register (OCS0 to OCS2) ............169
INDEX
463