Operation Of Communication Prescaler Register - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 16 COMMUNICATION PRESCALER REGISTER

16.2 Operation of Communication Prescaler Register

Set the communication prescaler register as follows, depending on the machine clock
φ used. For more information, see Section "17.4 UART Operations" and Section "18.3
Operation of I/O Extended Serial Interface".
■ Operation of Communication Prescaler Register
Table 16.2-1 Operation of Communication Prescaler Register
Machine clock φ
4 MHz
6 MHz
8 MHz
6 MHz
8 MHz
10 MHz
12 MHz
14 MHz
16 MHz
8 MHz
12MHz
16MHz
Confirm that φ divided by div does not exceed 4.25 MHz if setting a machine clock and div
different than the above.
256
div DIV3
4 1
6 1
8 1
3 1
4 1
5 1
6 1
7 1
8 1
2 1
3 1
4 1
DIV2 DIV1
1 0
0 1
0 0
1 0
1 0
0 1
0 1
0 0
0 0
1 1
1 0
1 0
φ/div
DIV0
0 1 MHz
0
0
1 2 MHz
0
1
0
1
0
0 4 MHz
1
0