Fujitsu F2MC-16LX Hardware Manual page 295

17.4 UART Operations
Figure 17.4-8 TDRE Setting Timing (Modes 0 and 1)
Write into SODR
TDRE
Requests an interrupt to CPU.
SOT interrupt
SOT output
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3
ST SP SP ST
A/D
D0 to D7 : Data bit A/D: Address/data multiplexer
ST: Start bit
SP: Stop bit
Figure 17.4-9 TDRE Setting Timing (mode 2)
Write into SODR
TDRE
Requests an interrupt to CPU.
SOT interrupt
SOT output
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6
D0 to D7: Data bit
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