Fujitsu F2MC-16LX Hardware Manual page 290

CHAPTER 17 UART
Non-communication period
SIN
(01010101 transmission)
B
RXE
Receiving
clock
Sampling clock
Recognition by the microcomputer
(01010101 reception)
B
Note that if receive ready is set at the timing represented in the following example, input data
(SIN) is not recognized correctly by the microcomputer:
• Example of operation where receive ready (RXE=H) is set while the communication line is at
L
Non-communication period
SIN
(01010101 transmission)
B
RXE
Receiving
clock
Sampling clock
Recognition by the microcomputer
(01010101 reception)
B
PE,ORE,FRE
■ Transmitter Operation
When the TDRE flag of the SSR register is set to "1", transmitter data is written into the SODR
register. If the TXE bit of the SCR register is "1" at this time, the data is transmitted.
When the data set in the SODR register is loaded into the transmitter shift register and begins to
be transmitted, the TDRE flag is set again and the next transmitter data can be set. If the TIE
bit of the SSR register is set to "1" at this time, a transmitter interrupt occurs to the CPU to
request the SODR register to set transmitter data.
The TDRE flag is cleared once when the data is set to the SODR register.
274
Figure 17.4-2 Normal Operation
Start bit
Mark level
ST D1
D0
• Receiving clock (8 pulses) • Sampling clock is generated by dividing the receiving clock by 16.
ST D1
D0
Figure 17.4-3 Abnormal Operation
Mark level Start bit
ST D1
D0
ST D0 D2
D1
recognition
Communication period
Data
D5
D3
D2 D4 D6
D3 D5
D2 D4 D6
Communication period
Data
D3 D5
D2 D4 D6
D4 D6
D3 D5 D7
Non-communication period
Stop bit
D7
SP
D7
SP
Non-communication period
Stop bit
D7
SP
SP
• Receive error occurs.