Reload Register (Iwdg_Rlr) - ST STM32F413 Reference Manual

Advanced arm-based 32-bit mcus

Hide thumbs Also See for STM32F413:

Reload register (IWDG_RLR)

Address offset: 0x08

Reset value: 0x0000 0FFF (reset by Standby mode)

Bits 31:12 Reserved, must be kept at reset value.

Bits11:0 RL[11:0]: Watchdog counter reload value

Note: Reading this register returns the reload value from the VDD voltage domain. This value

Status register (IWDG_SR)

Address offset: 0x0C

Reset value: 0x0000 0000 (not reset by Standby mode)

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 RVU: Watchdog counter reload value update

Bit 0 PVU: Watchdog prescaler value update

These bits are write access protected see

define the value to be loaded in the watchdog counter each time the value AAAAh is written

in the IWDG_KR register. The watchdog counter counts down from this value. The timeout

period is a function of this value and the clock prescaler. Refer to

The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload

may not be up to date/valid if a write operation to this register is ongoing on this

in the IWDG_SR register is reset.

This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset

by hardware when the reload value update operation is completed in the V

(takes up to 5 RC 40 kHz cycles).

Reload value can be updated only when RVU bit is reset.

This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is

reset by hardware when the prescaler update operation is completed in the V

domain (takes up to 5 RC 40 kHz cycles).

Prescaler value can be updated only when PVU bit is reset.

DocID029473 Rev 3

Independent watchdog (IWDG)

22.3.2. They are written by software to

voltage domain