Dma Introduction - ST STM32F413 Reference Manual

RM0430
9 Direct memory access controller (DMA)
9.1

DMA introduction

Direct memory access (DMA) is used in order to provide high-speed data transfer between
peripherals and memory and between memory and memory. Data can be quickly moved by
DMA without any CPU action. This keeps CPU resources free for other operations.
The DMA controller combines a powerful dual AHB master bus architecture with
independent FIFO to optimize the bandwidth of the system, based on a complex bus matrix
architecture.
The two DMA controllers have 16 streams in total (8 for each controller), each dedicated to
managing memory access requests from one or more peripherals. Each stream can have
up to 16 channels (requests) in total. And each has an arbiter for handling the priority
between DMA requests.
9.2 DMA main features
The main DMA features are:
•
Dual AHB master bus architecture, one dedicated to memory accesses and one
dedicated to peripheral accesses
•
AHB slave programming interface supporting only 32-bit accesses
•
8 streams for each DMA controller, up to 16 channels (requests) per stream
•
Four-word depth 32 first-in, first-out memory buffers (FIFOs) per stream, that can be
used in FIFO mode or direct mode:
–
–
• Each stream can be configured by hardware to be:
–
–
•
Each of the 8 streams are connected to dedicated hardware DMA channels (requests)
•
Priorities between DMA stream requests are software-programmable (4 levels
consisting of very high, high, medium, low) or hardware in case of equality (request 0
has priority over request 1, etc.)
FIFO mode: with threshold level software selectable between 1/4, 1/2 or 3/4 of the
FIFO size
Direct mode
Each DMA request immediately initiates a transfer from/to the memory. When it is
configured in direct mode (FIFO disabled), to transfer data in memory-to-
peripheral mode, the DMA preloads only one data from the memory to the internal
FIFO to ensure an immediate data transfer as soon as a DMA request is triggered
by a peripheral.
a regular channel that supports peripheral-to-memory, memory-to-peripheral and
memory-to-memory transfers
a double buffer channel that also supports double buffering on the memory side
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