Quadspi Device Configuration Register (Quadspi_Dcr) - ST STM32F413 Reference Manual

RM0430
12.5.2

QUADSPI device configuration register (QUADSPI_DCR)

Address offset: 0x0004
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31: 21 Reserved, must be kept at reset value.
Bits 20: 16 FSIZE[4:0]: Flash memory size
Bits 15: 11 Reserved, must be kept at reset value.
Bits 10:8 CSHT[2:0]: Chip select high time
Bits 7: 1 Reserved, must be kept at reset value.
Bit 0 CKMODE: Mode 0 / mode 3
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res. CSHT
rw rw rw
This field defines the size of external memory using the following formula:
Number of bytes in Flash memory = 2
FSIZE+1 is effectively the number of address bits required to address the Flash
memory. The Flash memory capacity can be up to 4GB (addressed using 32 bits) in
indirect mode, but the addressable space in memory-mapped mode is limited to
256MB.
If DFM = 1, FSIZE indicates the total capacity of the two Flash memories together.
This field can be modified only when BUSY = 0.
CSHT+1 defines the minimum number of CLK cycles which the chip select (nCS) must
remain high between commands issued to the Flash memory.
0: nCS stays high for at least 1 cycle between Flash memory commands
1: nCS stays high for at least 2 cycles between Flash memory commands
...
7: nCS stays high for at least 8 cycles between Flash memory commands
This field can be modified only when BUSY = 0.
This bit indicates the level that CLK takes between commands (when nCS = 1).
0: CLK must stay low while nCS is high (chip select released). This is referred to as
mode 0.
1: CLK must stay high while nCS is high (chip select released). This is referred to as
mode 3.
This field can be modified only when BUSY = 0.
DocID029473 Rev 3
Quad-SPI interface (QUADSPI)
23 22 21 20
Res. Res. Res.
rw
7 6 5 4
Res. Res. Res. Res.
[FSIZE+1]
19 18 17 16
FSIZE
rw rw rw rw
3 2 1
CK-
Res. Res. Res.
MODE
rw
323/1284
0
332