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RM0430
22.4
IWDG registers
Refer to
The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).
22.4.1
Key register (IWDG_KR)
Address offset: 0x00
Reset value: 0x0000 0000 (reset by Standby mode)
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
w
w
w
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 KEY[15:0]: Key value (write only, read 0000h)
Section 1.1 on page 51
27
26
25
Res.
Res.
Res.
11
10
9
w
w
w
w
These bits must be written by software at regular intervals with the key value AAAAh,
otherwise the watchdog generates a reset when the counter reaches 0.
Writing the key value 5555h to enable access to the IWDG_PR and IWDG_RLR registers
(see
Section
22.3.2)
Writing the key value CCCCh starts the watchdog (except if the hardware watchdog option is
selected)
for a list of abbreviations used in register descriptions.
24
23
22
Res.
Res.
Res.
8
7
6
KEY[15:0]
w
w
w
DocID029473 Rev 3
Independent watchdog (IWDG)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
w
w
w
w
17
16
Res.
Res.
1
0
w
w
669/1284
672
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