Sdio Command Response Register (Sdio_Respcmd) - ST STM32F413 Reference Manual

Advanced arm-based 32-bit mcus

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Secure digital input/output interface (SDIO)

Bit 8 WAITINT: CPSM waits for interrupt request

Bits 7:6 WAITRESP: Wait for response bits

Bits 5:0 CMDINDEX: Command index

The command index is sent to the card as part of a command message.

After a data write, data cannot be written to this register for three SDIOCLK clock periods

plus two PCLK2 clock periods.

MultiMediaCards can send two kinds of response: short responses, 48 bits long, or long

responses,136 bits long. SD card and SD I/O card can send only short responses, the

argument can vary according to the type of response: the software will distinguish the type

of response according to the sent command.

SDIO command response register (SDIO_RESPCMD)

Address offset: 0x10

Reset value: 0x0000 0000

The SDIO_RESPCMD register contains the command index field of the last command

response received. If the command response transmission does not contain the command

index field (long or OCR response), the RESPCMD field is unknown, although it must

contain 111111b (the value of the reserved field from the response).

Bits 31:6 Reserved, must be kept at reset value.

Bits 5:0 RESPCMD: Response command index

Read-only bit field. Contains the command index of the last command response received.

SDIO response 1..4 register (SDIO_RESPx)

Address offset: (0x10 + (4 × x)); x = 1..4

Reset value: 0x0000 0000

The SDIO_RESP1/2/3/4 registers contain the status of a card, which is part of the received

If this bit is set, the CPSM disables command timeout and waits for an interrupt request.

They are used to configure whether the CPSM is to wait for a response, and if yes, which

kind of response.

00: No response, expect CMDSENT flag

01: Short response, expect CMDREND or CCRCFAIL flag

10: No response, expect CMDSENT flag

11: Long response, expect CMDREND or CCRCFAIL flag

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