Fmpi2C_Timingr Register Configuration Examples - ST STM32F413 Reference Manual

Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
26.4.9

FMPI2C_TIMINGR register configuration examples

The tables below provide examples of how to program the FMPI2C_TIMINGR to obtain
timings compliant with the I
values, please refer to the application note: I
associated software STSW-STM32126.
26.4.10 SMBus specific features
This section is relevant only when SMBus feature is supported. Please refer to
FMPI2C
Introduction
The System Management Bus (SMBus) is a two-wire interface through which various
devices can communicate with each other and with the rest of the system. It is based on I
principles of operation. SMBus provides a control bus for system and power management
related tasks.
This peripheral is compatible with the SMBUS specification rev 2.0 (http://smbus.org).
The System Management Bus Specification refers to three types of devices.
• A slave is a device that receives or responds to a command.
•
A master is a device that issues commands, generates the clocks and terminates the
transfer.
•
A host is a specialized master that provides the main interface to the system's CPU. A
host must be a master-slave and must support the SMBus host notify protocol. Only
one host is allowed in a system.
This peripheral can be configured as master or slave device, and also as a host.
SMBUS is based on I
Bus protocols
There are eleven possible command protocols for any given device. A device may use any
or all of the eleven protocols to communicate. The protocols are Quick Command, Send
Byte, Receive Byte, Write Byte, Write Word, Read Byte, Read Word, Process Call, Block
Read, Block Write and Block Write-Block Read Process Call. These protocols should be
implemented by the user software.
For more details of these protocols, refer to SMBus specification version 2.0
(http://smbus.org).
Address resolution protocol (ARP)
SMBus slave address conflicts can be resolved by dynamically assigning a new unique
address to each slave device. In order to provide a mechanism to isolate each device for the
purpose of address assignment each device must implement a unique device identifier
(UDID). This 128-bit number is implemented by software.
This peripheral supports the Address Resolution Protocol (ARP). The SMBus Device
Default Address (0b1100 001) is enabled by setting SMBDEN bit in FMPI2C_CR1 register.
The ARP commands should be implemented by the user software.
Arbitration is also performed in slave mode for ARP support.
786/1284
2
C specification. In order to get more accurate configuration
implementation.
2
C specification rev 2.1.
DocID029473 Rev 3
2
C timing configuration tool (AN4235) and the
RM0430
Section 26.3:
2
C