Otg Interrupt Register (Otg_Gotgint) - ST STM32F413 Reference Manual

RM0430
Bit 3 VBVALOVAL: V
This bit is used to set override value for vbusvalid signal when VBVALOEN bit is set.
0: vbusvalid value is '0' when VBVALOEN = 1
1: vbusvalid value is '1' when VBVALOEN = 1
Note: Only accessible in host mode.
Bit 2 VBVALOEN: V
This bit is used to enable/disable the software to override the vbusvalid signal using the
VBVALOVAL bit.
0: Override is disabled and vbusvalid signal from the respective PHY selected is used
internally by the core
1: Internally vbusvalid received from the PHY is overridden with VBVALOVAL bit value
Note: Only accessible in host mode.
Bit 1 SRQ: Session request
The application sets this bit to initiate a session request on the USB. The application can
clear this bit by writing a 0 when the host negotiation success status change bit in the
OTG_GOTGINT register (HNSSCHG bit in OTG_GOTGINT) is set. The core clears this bit
when the HNSSCHG bit is cleared.
If you use the USB 1.1 full-speed serial transceiver interface to initiate the session request,
the application must wait until V
register (BSVLD bit in OTG_GOTGCTL) is cleared. This discharge time varies between
different PHYs and can be obtained from the PHY vendor.
0: No session request
1: Session request
Note: Only accessible in device mode.
Bit 0 SRQSCS: Session request success
The core sets this bit when a session request initiation is successful.
0: Session request failure
1: Session request success
Note: Only accessible in device mode.
33.15.2

OTG interrupt register (OTG_GOTGINT)

Address offset: 0x04
Reset value: 0x0000 0000
The application reads this register whenever there is an OTG interrupt and clears the bits in
this register to clear the OTG interrupt.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
valid override value.
BUS
valid override enable.
BUS
28 27 26 25
Res. Res. Res.
12 11 10 9
HNSS
Res. Res.
CHG
rc_w1
DocID029473 Rev 3
USB on-the-go full-speed (OTG_FS)
discharges to 0.2 V, after the B-Session Valid bit in this
BUS
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
SRSS
Res. Res. Res.
CHG
rc_w1
20 19 18 17
ID DBC ADTO HNG
CHNG DNE CHG DET
rc_w1
rc_w1 rc_w1 rc_w1
4 3 2
Res. Res. SEDET Res.
rc_w1
16
Res.
1 0
Res.
1127/1284
1245