ST STM32F413 Reference Manual page 1159

RM0430
Bit 2 PENA: Port enable
A port is enabled only by the core after a reset sequence, and is disabled by an overcurrent
condition, a disconnect condition, or by the application clearing this bit. The application
cannot set this bit by a register write. It can only clear it to disable the port. This bit does not
trigger any interrupt to the application.
0: Port disabled
1: Port enabled
Bit 1 PCDET: Port connect detected
The core sets this bit when a device connection is detected to trigger an interrupt to the
application using the host port interrupt bit in the Core interrupt register (HPRTINT bit in
OTG_GINTSTS). The application must write a 1 to this bit to clear the interrupt.
Bit 0 PCSTS: Port connect status
0: No device is attached to the port
1: A device is attached to the port
33.15.25 OTG Host channel-x characteristics register (OTG_HCCHARx)
(x = 0..11, where x = Channel_number)
Address offset: 0x500 + (Channel_number × 0x20)
Reset value: 0x0000 0000
31 30 29
ODD
CHENA CHDIS
FRM
rs rs rw
15 14 13
EPDIR EPNUM
rw rw rw
Bit 31 CHENA: Channel enable
Bit 30 CHDIS: Channel disable
Bit 29 ODDFRM: Odd frame
Bits 28:22 DAD: Device address
28 27 26 25
DAD
rw rw rw rw
12 11 10 9
rw rw rw rw
This field is set by the application and cleared by the OTG host.
0: Channel disabled
1: Channel enabled
The application sets this bit to stop transmitting/receiving data on a channel, even before
the transfer for that channel is complete. The application must wait for the Channel disabled
interrupt before treating the channel as disabled.
This field is set (reset) by the application to indicate that the OTG host must perform a
transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt)
transactions.
0: Even frame
1: Odd frame
This field selects the specific device serving as the data source or sink.
24 23 22
rw rw rw
8 7 6
rw rw rw
DocID029473 Rev 3
USB on-the-go full-speed (OTG_FS)
21 20 19 18
MCNT EPTYP
rw rw rw rw
5 4 3
MPSIZ
rw rw rw rw
17 16
LSDEV Res.
rw
2 1 0
rw rw
1159/1284
1245