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RM0430
20.4.4
TIM6/7 status register (TIMx_SR)
Address offset: 0x10
Reset value: 0x0000
15
14
13
Res.
Res.
Res.
Res.
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 UIF: Update interrupt flag
– At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the
– When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0
20.4.5
TIM6/7 event generation register (TIMx_EGR)
Address offset: 0x14
Reset value: 0x0000
15
14
13
Res.
Res.
Res.
Res.
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Re-initializes the timer counter and generates an update of the registers. Note that the
prescaler counter is cleared too (but the prescaler ratio is not affected).
20.4.6
TIM6/7 counter (TIMx_CNT)
Address offset: 0x24
Reset value: 0x0000
15
14
13
rw
rw
rw
Bits 15:0
CNT[15:0]: Counter value
12
11
10
9
Res.
Res.
Res.
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
TIMx_CR1 register.
and UDIS = 0 in the TIMx_CR1 register.
12
11
10
9
Res.
Res.
Res.
12
11
10
9
rw
rw
rw
rw
8
7
6
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
8
7
6
CNT[15:0]
rw
rw
rw
DocID029473 Rev 3
Basic timers (TIM6/7)
5
4
3
2
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
5
4
3
2
rw
rw
rw
rw
1
0
Res.
UIF
rc_w0
1
0
Res.
UG
w
1
0
rw
rw
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