Sdio Data Counter Register (Sdio_Dcount) - ST STM32F413 Reference Manual

Advanced arm-based 32-bit mcus

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Secure digital input/output interface (SDIO)

SDIO data counter register (SDIO_DCOUNT)

Address offset: 0x30

Reset value: 0x0000 0000

The SDIO_DCOUNT register loads the value from the data length register (see

SDIO_DLEN) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As

data is transferred, the counter decrements the value until it reaches 0. The DPSM then

moves to the Idle state and the data status end flag, DATAEND, is set.

Bits 31:25 Reserved, must be kept at reset value.

Bits 24:0 DATACOUNT: Data count value

When this bit is read, the number of remaining data bytes to be transferred is returned. Write

has no effect.

This register should be read only when the data transfer is complete.

SDIO status register (SDIO_STA)

Address offset: 0x34

Reset value: 0x0000 0000

The SDIO_STA register is a read-only register. It contains two types of flag:

Static flags (bits [23:22,10:0]): these bits remain asserted until they are cleared by

writing to the SDIO Interrupt Clear register (see SDIO_ICR)

Dynamic flags (bits [21:11]): these bits change state depending on the state of the

underlying logic (for example, FIFO full and empty flags are asserted and deasserted

as data while written to the FIFO)

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 SDIOIT: SDIO interrupt received

Bit 21 RXDAVL: Data available in receive FIFO

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DATACOUNT[15:0]

DATACOUNT[24:16]