Rcc Clocks Gated Enable Register (Ckgatenr) - ST STM32F413 Reference Manual

Reset and clock control (RCC) for STM32F413/423
6.3.28

RCC clocks gated enable register (CKGATENR)

Address offset: 0x90
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
This register allows to enable or disable the clock gating for the specified IPs.
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 EVTCL_CKEN
Bit 6 RCC_CKEN: RCC clock enable
Bit 5 FLITF_CKEN: Flash Interface clock enable
Bit 4 SRAM_CKEN: SRAM (SRAM1 and SRAM2) controller clock enable
Bit 3 SPARE_CKEN: Spare clock enable
Bit 2 CM4DBG_CKEN: Cortex M4 ETM clock enable
Bit 1 AHB2APB2_CKEN: AHB to APB2 Bridge clock enable
Bit 0 AHB2APB1_CKEN: AHB to APB1 Bridge clock enable
176/1284
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res. Res. Res. Res.
0: the clock gating is enabled
1: the cock gating is disabled, the clock is always enabled
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
23 22 21
Res. Res. Res.
7 6 5
EVTCL RCC FLITF
_CKEN _CKEN _CKEN
rw rw rw
DocID029473 Rev 3
20 19 18
Res. Res. Res.
4 3 2
SRAM SPARE CM4DBG AHB2APB2
_CKEN _CKEN _CKEN
rw rw rw
RM0430
17 16
Res. Res.
1 0
AHB2APB1
_CKEN _CKEN
rw rw