ST STM32F413 Reference Manual page 752

Real-time clock (RTC)
Offset Register
RTC_SSR
0x28
Reset value
RTC_SHIFTR
0x2C
0
Reset value
RTC_TSTR
0x30
Reset value
RTC_TSSSR
0x38
Reset value
RTC_ CALR
0x3C
Reset value
RTC_
ALRMASSR
0x44
Reset value
RTC_
ALRMBSSR
0x48
Reset value
RTC_BKP0R
Reset value 0
0x50
to 0x9C
to
RTC_BKP19R
Reset value 0
Refer to
Caution: In Table
registers are not affected by a system reset. For more information, refer to
Resetting the
752/1284
Table 126. RTC register map and reset values (continued)
MASKSS[3:0]
0 0 0 0
MASKSS[3:0]
0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Section 2.2.2 on page 56
126, the reset value is the value after a backup domain reset. The majority of the
RTC.
0
HU[3:0]
0 0 0 0 0 0 0
0
0
BKP[31:0]
0 0 0 0 0 0 0 0
BKP[31:0]
0 0 0 0 0 0 0 0
for the register boundary addresses.
DocID029473 Rev 3
SS[15:0]
0 0 0 0 0 0 0 0 0
SUBFS[14:0]
0 0 0 0 0 0 0 0 0
MNU[3:0] ST[2:0]
0 0 0 0 0 0 0 0
SS[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0
SS[14:0]
0 0 0 0 0 0 0 0 0
SS[14:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
Section 25.3.7:
RM0430
0 0 0 0 0 0
0 0 0 0 0 0
SU[3:0]
0 0 0 0 0 0
0 0 0 0 0 0
CALM[8:0]
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0