Rtc Alarm A Sub Second Register (Rtc_Alrmassr) - ST STM32F413 Reference Manual

RM0430
Bit 1 TAMP1TRG: Active level for tamper 1
if TAMPFLT != 00:
0: TAMPER1 staying low triggers a tamper detection event.
1: TAMPER1 staying high triggers a tamper detection event.
if TAMPFLT = 00:
0: TAMPER1 rising edge triggers a tamper detection event.
1: TAMPER1 falling edge triggers a tamper detection event.
Caution: When TAMPFLT = 0, TAMP1E must be reset when TAMP1TRG is changed to avoid
Bit 0 TAMP1E: Tamper 1 detection enable
0: Tamper 1 detection disabled
1: Tamper 1 detection enabled
25.6.18

RTC alarm A sub second register (RTC_ALRMASSR)

Address offset: 0x44
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
Res. Res. Res. Res.
15 14 13
Res.
rw rw
Bits 31:28 Reserved, must be kept at reset value
Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit
Bits 23:15 Reserved, must be kept at reset value
Bits 14:0 SS[14:0]: Sub seconds value
spuriously setting TAMP1F.
28 27 26 25
MASKSS[3:0]
rw rw rw
12 11 10 9
rw rw rw rw
0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is
incremented (assuming that the rest of the fields match).
1: SS[14:1] are don't care in Alarm A comparison. Only SS[0] is compared.
2: SS[14:2] are don't care in Alarm A comparison. Only SS[1:0] are compared.
3: SS[14:3] are don't care in Alarm A comparison. Only SS[2:0] are compared.
...
12: SS[14:12] are don't care in Alarm A comparison. SS[11:0] are compared.
13: SS[14:13] are don't care in Alarm A comparison. SS[12:0] are compared.
14: SS[14] is don't care in Alarm A comparison. SS[13:0] are compared.
15: All 15 SS bits are compared and must match to activate alarm.
The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be
different from 0 only after a shift operation.
This value is compared with the contents of the synchronous prescaler's counter to
determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared.
DocID029473 Rev 3
24 23 22 21
Res. Res. Res.
rw
8 7 6 5
SS[14:0]
rw rw rw rw
Real-time clock (RTC)
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
rw rw w rw
16
Res.
0
rw
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