Spi Functional Description - ST STM32F413 Reference Manual

RM0430
29.3

SPI functional description

29.3.1 General description
The SPI allows synchronous, serial communication between the MCU and external devices.
Application software can manage the communication by polling the status flag or using
dedicated SPI interrupt. The main elements of SPI and their interactions are shown in the
following block diagram
Four I/O pins are dedicated to SPI communication with external devices.
•
MISO: Master In / Slave Out data. In the general case, this pin is used to transmit data
in slave mode and receive data in master mode.
•
MOSI: Master Out / Slave In data. In the general case, this pin is used to transmit data
in master mode and receive data in slave mode.
•
SCK: Serial Clock output pin for SPI masters and input pin for SPI slaves.
•
NSS: Slave select pin. Depending on the SPI and NSS settings, this pin can be used to
either:
–
–
–
See
The SPI bus allows the communication between one master device and one or more slave
devices. The bus consists of at least two wires - one for the clock signal and the other for
synchronous data transfer. Other signals can be added depending on the data exchange
between SPI nodes and their slave select signal management.
Figure
Figure 305. SPI block diagram
select an individual slave device for communication
synchronize the data frame or
detect a conflict between multiple masters
Section 29.3.5: Slave select (NSS) pin management
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Serial peripheral interface/ inter-IC sound (SPI/I2S)
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for details.
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