Table 57. Fsmc_Bwtrx Bit Fields - ST STM32F413 Reference Manual

Flexible static memory controller (FSMC)
Bit number
31:30
29:28
27:24
23:20
19:16
15:8
7:4
3:0
Note: The FSMC_BWTRx register is valid only if the extended mode is set (mode B), otherwise its
content is don't care.
Mode C - NOR Flash - OE toggling
278/1284

Table 57. FSMC_BWTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x1 if extended mode is set
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the access second phase (DATAST HCLK cycles) for
DATAST
write accesses.
ADDHLD Don't care
Duration of the access first phase (ADDSET HCLK cycles) for write
ADDSET
accesses. Minimum value for ADDSET is 0.
Figure 40. ModeC read access waveforms
DocID029473 Rev 3
Value to set
RM0430