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ST STM32F413 Reference Manual page 1161

Advanced arm-based 32-bit mcus
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RM0430
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 DTERR: Data toggle error
Bit 9 FRMOR: Frame overrun
Bit 8 BBERR: Babble error
Bit 7 TXERR: Transaction error
Indicates one of the following errors occurred on the USB.
CRC check failure
Timeout
Bit stuff error
False EOP
Bit 6 Reserved, must be kept at reset value .
Bit 5 ACK: ACK response received/transmitted interrupt
Bit 4 NAK: NAK response received interrupt
Bit 3 STALL: STALL response received interrupt
Bit 2 Reserved, must be kept at reset value .
Bit 1 CHH: Channel halted
Indicates the transfer completed abnormally either because of any USB transaction error or
in response to disable request by the application.
Bit 0 XFRC: Transfer completed
Transfer completed normally without any errors.
33.15.27 OTG Host channel-x interrupt mask register (OTG_HCINTMSKx)
(x = 0..11, where x = Channel_number)
Address offset: 0x50C + (Channel_number × 0x20)
Reset value: 0x0000 0000
This register reflects the mask for each channel status described in the previous section.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
DTERR
FRM
Res.
M
ORM
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DocID029473 Rev 3
USB on-the-go full-speed (OTG_FS)
24
23
22
Res.
Res.
Res.
Res.
8
7
6
BBERR
TXERR
Res.
ACKM
M
M
rw
rw
21
20
19
18
Res.
Res.
Res.
5
4
3
2
STALL
NAKM
Res.
M
rw
rw
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17
16
Res.
Res.
1
0
XFRC
CHHM
M
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