ST STM32F413 Reference Manual page 321

RM0430
Bit 18 FTIE: FIFO threshold interrupt enable
Bit 17 TCIE: Transfer complete interrupt enable
Bit 16 TEIE: Transfer error interrupt enable
Bits 15:13 Reserved, must be kept at reset value.
Bits 12:8 FTHRES[4:0] FIFO threshold level
Bit 7 FSEL: Flash memory selection
Bit 6 DFM: Dual-flash mode
Bit 5 Reserved, must be kept at reset value.
This bit enables the FIFO threshold interrupt.
0: Interrupt disabled
1: Interrupt enabled
This bit enables the transfer complete interrupt.
0: Interrupt disabled
1: Interrupt enabled
This bit enables the transfer error interrupt.
0: Interrupt disable
1: Interrupt enabled
Defines, in indirect mode, the threshold number of bytes in the FIFO that will cause the
FIFO threshold flag (FTF, QUADSPI_SR[2]) to be set.
In indirect write mode (FMODE = 00):
0: FTF is set if there are 1 or more free bytes available to be written to in the FIFO
1: FTF is set if there are 2 or more free bytes available to be written to in the FIFO
...
31: FTF is set if there are 32 free bytes available to be written to in the FIFO
In indirect read mode (FMODE = 01):
0: FTF is set if there are 1 or more valid bytes that can be read from the FIFO
1: FTF is set if there are 2 or more valid bytes that can be read from the FIFO
...
31: FTF is set if there are 32 valid bytes that can be read from the FIFO
If DMAEN = 1, then the DMA controller for the corresponding channel must be disabled
before changing the FTHRES value.
This bit selects the Flash memory to be addressed in single flash mode (when DFM =
0).
0: FLASH 1 selected
1: FLASH 2 selected
This bit can be modified only when BUSY = 0.
This bit is ignored when DFM = 1.
This bit activates dual-flash mode, where two external Flash memories are used
simultaneously to double throughput and capacity.
0: Dual-flash mode disabled
1: Dual-flash mode enabled
This bit can be modified only when BUSY = 0.
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Quad-SPI interface (QUADSPI)
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