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ST STM32F413 Reference Manual page 428

Advanced arm-based 32-bit mcus
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Digital filter for sigma delta modulators (DFSDM)
Bits 31:8 JDATA[23:0]: Injected group conversion data
When each conversion of a channel in the injected group finishes, its resulting data is stored in this
field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 JDATACH[2:0]: Injected channel most recently converted
When each conversion of a channel in the injected group finishes, JDATACH[2:0] is updated to
indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the
channel indicated by JDATACH[2:0].
Note:
DMA may be used to read the data from this register. Half-word accesses may be used to
read only the MSBs of conversion data.
Reading this register also clears JEOCF in DFSDM_FLTxISR. Thus, the firmware must not
read this register if DMA is activated to read data from this register.
15.8.8
DFSDM data register for the regular channel
(DFSDM_FLTxRDATAR)
Address offset: 0x11C + 0x80 * x, x = 0...3
Reset value: 0x0000 0000
31
30
29
15
14
13
r
r
r
Bits 31:8 RDATA[23:0]: Regular channel conversion data
When each regular conversion finishes, its data is stored in this register. The data is valid when
REOCF=1. Reading this register clears the corresponding REOCF.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 RPEND: Regular channel pending data
Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 RDATACH[2:0]: Regular channel most recently converted
When each regular conversion finishes, RDATACH[2:0] is updated to indicate which channel was
converted (because regular channel selection RCH[2:0] in DFSDM_FLTxCR1 register can be
updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the
channel indicated by RDATACH[2:0].
Note:
Half-word accesses may be used to read only the MSBs of conversion data.
Reading this register also clears REOCF in DFSDM_FLTxISR.
428/1284
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27
26
25
12
11
10
9
RDATA[7:0]
r
r
r
r
DocID029473 Rev 3
24
23
22
21
RDATA[23:8]
8
7
6
5
Res.
Res.
Res.
r
20
19
18
4
3
2
RPEND
Res.
RDATACH[2:0]
r
r
RM0430
17
16
1
0
r
r

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