Dfsdm Reset And Clocks - ST STM32F413 Reference Manual

Advanced arm-based 32-bit mcus

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Digital filter for sigma delta modulators (DFSDM)

dfsdm_jtrg10

dfsdm_break[0]

dfsdm_break[1]

dfsdm_break[2]

dfsdm_break[3]

DFSDM reset and clocks

DFSDM on-off control

The DFSDM interface is globally enabled by setting DFSDMEN=1 in the

DFSDM_CH0CFGR1 register. Once DFSDM is globally enabled, all input channels (y=0..7)

and digital filters DFSDM_FLTx (x=0..3) start to work if their enable bits are set (channel

enable bit CHEN in DFSDM_CHyCFGR1 and DFSDM_FLTx enable bit DFEN in

DFSDM_FLTxCR1).

Digital filter x DFSDM_FLTx (x=0..3) is enabled by setting DFEN=1 in the

DFSDM_FLTxCR1 register. Once DFSDM_FLTx is enabled (DFEN=1), both Sinc

filter unit and integrator unit are reinitialized.

By clearing DFEN, any conversion which may be in progress is immediately stopped and

DFSDM_FLTx is put into stop mode. All register settings remain unchanged except

DFSDM_FLTxAWSR and DFSDM_FLTxISR (which are reset).

Channel y (y=0..7) is enabled by setting CHEN=1 in the DFSDM_CHyCFGR1 register.

Once the channel is enabled, it receives serial data from the external Σ∆ modulator or

parallel internal data sources (CPU/DMA wire from memory).

DFSDM must be globally disabled (by DFSDMEN=0 in DFSDM_CH0CFGR1) before

stopping the system clock to enter in the STOP mode of the device.

Table 86. DFSDM2 triggers connection

Trigger name

Table 87. DFSDM break connection

DocID029473 Rev 3

Trigger source

Break destination