Dma Transactions - ST STM32F413 Reference Manual

Direct memory access controller (DMA)
9.3.3

DMA transactions

A DMA transaction consists of a sequence of a given number of data transfers. The number
of data items to be transferred and their width (8-bit, 16-bit or 32-bit) are software-
programmable.
Each DMA transfer consists of three operations:
•
A loading from the peripheral data register or a location in memory, addressed through
the DMA_SxPAR or DMA_SxM0AR register
•
A storage of the data loaded to the peripheral data register or a location in memory
addressed through the DMA_SxPAR or DMA_SxM0AR register
•
A post-decrement of the DMA_SxNDTR register, which contains the number of
transactions that still have to be performed
After an event, the peripheral sends a request signal to the DMA controller. The DMA
controller serves the request depending on the channel priorities. As soon as the DMA
controller accesses the peripheral, an Acknowledge signal is sent to the peripheral by the
DMA controller. The peripheral releases its request as soon as it gets the Acknowledge
signal from the DMA controller. Once the request has been deasserted by the peripheral,
the DMA controller releases the Acknowledge signal. If there are more requests, the
peripheral can initiate the next transaction.
9.3.4 Channel selection
Each stream is associated with a DMA request that can be selected out of 16 possible
channel requests. The selection is controlled by the CHSEL[3:0] bits in the DMA_SxCR
register.
The 16 requests from the peripherals (TIM, ADC, SPI, I2C, etc.) are independently
connected to each channel and their connection depends on the product implementation.
Table 30
214/1284
Figure 24. Channel selection
and Table 31 give examples of DMA request mappings.
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