Reception Handling - ST STM32F413 Reference Manual

Controller area network (bxCAN)
and Tx mailboxes). The internal counter is incremented each CAN bit time (refer to
Section 32.7.7: Bit
Of Frame bit in both reception and transmission.
32.7.3

Reception handling

For the reception of CAN messages, three mailboxes organized as a FIFO are provided. In
order to save CPU load, simplify the software and guarantee data consistency, the FIFO is
managed completely by hardware. The application accesses the messages stored in the
FIFO through the FIFO output mailbox.
Valid message
A received message is considered as valid when it has been received correctly according to
the CAN protocol (no error until the last but one bit of the EOF field) and It passed through
the identifier filtering successfully, see
FIFO management
Starting from the empty state, the first valid message received is stored in the FIFO which
becomes pending_1. The hardware signals the event setting the FMP[1:0] bits in the
1060/1284
timing). The internal counter is captured on the sample point of the Start
Section 32.7.4: Identifier
Figure 371. Receive FIFO states
DocID029473 Rev 3
RM0430
filtering.