Dma Stream X Fifo Control Register (Dma_Sxfcr) (X = 0..7) - ST STM32F413 Reference Manual

Advanced arm-based 32-bit mcus

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Direct memory access controller (DMA)

Bits 31:0 M1A[31:0]: Memory 1 address (used in case of Double buffer mode)

DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7)

Address offset: 0x24 + 0x24 × stream number

Reset value: 0x0000 0021

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 FEIE: FIFO error interrupt enable

Bit 6 Reserved, must be kept at reset value.

Bits 5:3 FS[2:0]: FIFO status

Base address of Memory area 1 from/to which the data will be read/written.

This register is used only for the Double buffer mode.

These bits are write-protected. They can be written only if:

the stream is disabled (bit EN= '0' in the DMA_SxCR register) or

the stream is enabled (EN='1' in DMA_SxCR register) and bit CT = '0' in the

DMA_SxCR register.

This bit is set and cleared by software.

0: FE interrupt disabled

1: FE interrupt enabled

These bits are read-only.

000: 0 < fifo_level < 1/4

001: 1/4 ≤ fifo_level < 1/2

010: 1/2 ≤ fifo_level < 3/4

011: 3/4 ≤ fifo_level < full

100: FIFO is empty

101: FIFO is full

others: no meaning

These bits are not relevant in the direct mode (DMDIS bit is zero).

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