Oversampling By 16 - ST STM32F413 Reference Manual

RM0430
Table 151. Error calculation for programmed baud rates at f
Baud rate
S.No Desired

1.

2.4 KBps
2. 9.6 KBps
3. 19.2 KBps
4. 57.6 KBps
5. 115.2 KBps
6. 230.4 KBps
7. 460.8 KBps
8. 896 KBps
9. 921.6 KBps
10. 1.792 MBps
11. 1.8432 MBps
12. 3.584 MBps
13. 3.6864 MBps
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.
2. Only USART1 and USART6 are clocked with PCLK2. Other USARTs are clocked with PCLK1. Refer to the device
datasheets for the maximum values for PCLK1 and PCLK2.
Table 152. Error calculation for programmed baud rates at f
Baud rate
S.No Desired
1. 2.4 KBps
2. 9.6 KBps
3. 19.2 KBps
4. 57.6 KBps
Universal synchronous asynchronous receiver transmitter (USART)

oversampling by 16

Oversampling by 16 (OVER8=0)
f = 30 MHz
PCLK
Value
programme
Actual d in the
baud rate
register
2.400 KBps 781.2500
9.600 KBps 195.3125
19.194 KBps 97.6875
57.582KBps 32.5625
115.385 KBps 16.2500
230.769 KBps 8.1250
461.538 KBps 4.0625
909.091 KBps 2.0625
909.091 KBps 2.0625
1.1764 MBps 1.0625
1.8750 MBps 1.0000
NA NA
NA NA
oversampling by 8
Oversampling by 8 (OVER8=1)
f = 30 MHz
PCLK
Value
programme
Actual d in the
baud rate
register
2.400 KBps 1562.5000
9.600 KBps 390.6250
19.194 KBps 195.3750
57.582 KBps 65.1250
DocID029473 Rev 3
PCLK
(1)(2)
% Error =
(Calculated -
Actual
Desired)B.Rate
/Desired B.Rate
0.00% 2.400 KBps
0.00% 9.600 KBps
0.03% 19.200 KBps
0.03% 57.582 KBps
0.16% 115.163 KBps
0.16% 230.769 KBps
0.16% 461.538 KBps
1.46% 895.522 KBps
1.36% 923.077 KBps
1.52% 1.8182 MBps
1.73% 1.8182 MBps
NA 3.2594 MBps
NA 3.7500 MBps
PCLK
(1) (2)
% Error =
(Calculated -
Actual
Desired)B.Rate
/Desired B.Rate
0.00% 2.400 KBps
0.00% 9.600 KBps
0.03% 19.200 KBps
0.16% 57.582 KBps
= 30 MHz or f = 60 MHz,
PCLK
f = 60 MHz
PCLK
Value
programmed
in the baud
rate register
1562.5000
390.6250
195.3125
65.1250
32.5625
16.2500
8.1250
4.1875
4.0625
2.0625
2.0625
1.0625
1.0000
= 30 MHz or f = 60 MHz,
PCLK
f =60 MHz
PCLK
Value
programmed
in the baud
rate register
3125.0000
781.2500
390.6250
130.2500
%
Error
0.00%
0.00%
0.00%
0.03%
0.03%
0.16%
0.16%
0.05%
0.16%
1.36%
1.52%
1.52%
1.73%
%
Error
0.00%
0.00%
0.00%
0.03%
875/1284
906