Aes Status Register (Aes_Sr) - ST STM32F413 Reference Manual

Advanced arm-based 32-bit mcus

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AES status register (AES_SR)

Address offset: 0x04

Reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 Busy: Busy flag

This bit is set and reset by hardware to indicate that higher priority message can interrupt the current

message during GCM payload phase for encryption mode only

0: GCM suspend mode can perform

1: GCM suspend mode cannot perform

Note: This bit has effect only when GCM algorithm is selected.

Note: This flag has no effect when GCM is configured in GCM init phase, GCM header phase, GCM

payload phase (decryption mode) and GCM final phase.

Advanced encryption standard hardware accelerator (AES)

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