ST STM32F413 Reference Manual page 704

Advanced encryption standard hardware accelerator (AES)
Bit 9 CCFIE: CCF flag interrupt enable
An interrupt is generated if the CCF flag is set.
0: CCF interrupt disabled
1: CCF interrupt enabled
Bit 8 ERRC: Error clear
Writing 1 to this bit clears the RDERR and WRERR flags.
This bit is always read low.
Bit 7 CCFC: Computation complete flag clear
Writing 1 to this bit clears the CCF flag.
This bit is always read low.
Bit 16 and CHMOD[2:0]: AES chaining mode
Bits 6:5
000: Electronic codebook (ECB)
001: Cipher block chaining (CBC)
010: Counter mode (CTR)
011: Galois counter mode (GCM) and Galois message authentication code (GMAC)
100: Cipher message authentication code (CMAC)
The AES chaining mode must only be changed while the AES is disabled. Writing these bits while the
AES is enabled is forbidden in order to avoid unpredictable AES behavior.
Bits 4:3 MODE[1:0]: AES operating mode
00: Mode 1: Encryption
01: Mode 2: Key derivation
10: Mode 3: Decryption
11: Mode 4: Key derivation + decryption
The operation mode must only be changed if the AES is disabled. Writing these bits while the AES is
enabled is forbidden in order to avoid unpredictable AES behavior.
Mode 4 is forbidden if CTR mode/GCM mode is selected. It will be forced to mode 3 if the software,
nevertheless, attempts to set mode 4 for this CTR/GCM mode configuration.
Bits 2:1 DATATYPE[1:0]: Data type selection (for data in and data out to/from the cryptographic block)
00: 32-bit data. No swapping.
01: 16-bit data or half-word. In the word, each half-word is swapped. For example, if one of the four
32-bit data written in the AES_DINR register is 0x764356AB, the value given to the
cryptographic block is 0x56AB7643
10: 8-bit data or bytes. In the word, all the bytes are swapped. For example, if one of the four 32-bit
data written in the AES_DINR register is 0x764356AB, the value given to the cryptographic
block is 0xAB564376.
11: Bit data. In the word all the bits are swapped. For example, if one of the four 32-bit data written
in the AES_DINR register is 0x764356AB, the value given to the cryptographic block is
0xD56AC26E
The DATATYPE selection must be changed if the AES is disabled. Writing these bits while the AES is
enabled is forbidden to avoid unpredictable AES behavior.
Bit 0 EN: AES enable
0: AES disable
1: AES enable
The AES can be re-initialized at any moment by resetting this bit: the AES is then ready to start
processing a new block when EN is set.
This bit is cleared by hardware when the AES computation is finished in mode 2 (key derivation)
704/1284 DocID029473 Rev 3
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